Recently, concerning low voltage class power MOSFETs of 100 V or less, development of a power MOSFET having a trench gate (hereinafter, “power MOSFET”) is actively pursued aiming at reducing ON-resistance by reducing channel resistance. Various structures have been proposed for such a power MOSFET.
FIG. 21 is a cross-sectional view of components of a conventional power MOSFET. The power MOSFET includes an n− epitaxial layer (hereinafter, “n− epi layer”) 52 that is disposed on an n+ drain layer 51 and that is an n− drift layer; a p-channel layer (p-base layer) 53 that is disposed on a surface layer of the n− epi layer 52; an n+ source layer 61 and a p+ contact layer 64 that are disposed in a surface layer of the p-channel layer 53; a trench 57 that passes through the n+ source layer 61 and the p-channel layer 53 to the n− epi layer 52; a gate oxide film 59 that is disposed along an inner wall of the trench 57; a gate electrode 60a that is made of doped poly-silicon and that is embedded in the trench 57 through the gate oxide film 59; an interlayer insulating film 62a that is disposed on the gate electrode 60a and that fills an upper portion of the trench 57; a source electrode 65 that is disposed spanning across the n+ source layer 61, the p+ contact layer 64, and the interlayer insulating film 62a; and a drain electrode 66 that is disposed on a back face of the n+ drain layer 51 (see, e.g., Patent Literature 1 below).
A manufacturing method of the power MOSFET depicted in FIG. 21 will be described. After the p-channel layer 53 is formed, the trench 57 that passes from the p-channel layer 53 to the n− epi layer 52 is formed. The trench 57 is formed by dry etching using an oxide film (hereinafter, “CVD oxide film”) formed by chemical vapor deposition (CVD), as a mask. The gate oxide film 59 is formed in the trench 57 and the trench 57 is filled with poly-silicon forming the gate electrode 60a. The position of a surface of the gate electrode 60a is lower than a surface of the p-channel layer 53, a principal surface of the substrate. To form the n+ source layer 61, arsenic (As) ion is obliquely ion-implanted from a side wall of the trench 57 to the p-channel layer 53 using, as a mask, the CVD oxide film that is used to form the gate electrode 60a and the trench 57. Therefore, a diffusion source that forms the n+ source layer 61 is introduced into the side wall of the trench 57. The CVD oxide film is removed. A resist mask that has an opening corresponding to an area to form the p+ contact layer 64 is formed. Using this resist mask, boron (B) ion or boron fluoride (BF2) ion is implanted into a surface of the p-channel layer 53.
The impurity ion introduced into the surface of the p-channel layer 53 is activated by a heat treatment and thereby, the n+ source layer 61 and the p+ contact layer 64 are formed. The n+ source layer 61 is formed by a diffusion of arsenic having a short diffusion length diffused from the side wall of the trench 57. Therefore, the width (hereinafter, meaning a “lateral diffusion width”) w of a surface of the n+ source layer 61 that is exposed to the surface of the p-channel layer 53 becomes narrow. The interlayer insulating film 62a made of Boron Phosphor Silicate Glass (BPSG), etc., is deposited. The interlayer insulating film 62a is etched to the surface of the p-channel layer 53, the principal surface of the substrate. The source electrode 65 in contact with the n+ source layer 61 is formed using a metal such as aluminum (Al). The drain electrode 66 is formed on the posterior surface of the n+ drain layer 51 using a metal such as gold (Au).
A feature of the above manufacturing method is that the n+ source layer 61 is formed by self-alignment using the mask that is used to form the gate electrode 60a and the trench 57. As a result, effects described in (1) to (3) herein are obtained. (1) In forming the n+ source layer 61, any shift of the mask made during the patterning, any tolerance for etching back the gate electrode 60a, etc., do not need to be taken into account. (2) A cell may be downsized because the lateral diffusion width of the n+ source layer 61 can be reduced. (3) Because the n+ source layer 61 is formed using the gate electrode 60a as a mask, an overlapped portion of the gate and the source regions can be reduced and therefore, source-gate parasitic capacity can be reduced.
A method of forming an L-shaped source region by obliquely implanting ion using a resist mask having a narrower width than that of a mask for forming a trench has been proposed as another manufacturing method of a power MOSFET. The ion is implanted into the inside of the trench using a gate electrode as a mask. Therefore, a same effect as that in (3) above is obtained (see, e.g., Patent Literature 2 below).
A method of filling a recess on a gate electrode with a CVD oxide film and poly-silicon (to be oxidized) aiming at securely and stably obtaining a gate electrode layer and a cap insulating layer each having a predetermined thickness has been proposed as another method (see, e.g., Patent Literature 3 below).
A method of forming an n+ source layer by diffusing an impurity into an interlayer insulating film (Inter Layer Dielectrics (ILD)) has been proposed as another method. According to this method, the n+ source layer may be formed evenly along the direction of the thickness of a trench groove. The width of the n+ source layer along the direction of the trench width may be reduced. As a result, reduction of ON-resistance and finer processing can be facilitated (see, e.g., Patent Literature 4 to 6 below).
For electrical contact of a p-channel layer for which trench intervals are finely narrowed, a method of newly forming a trench to cross a gate trench, thereby, bringing a p-channel layer in electrical contact with a source electrode has been proposed as another method (see, e.g., Patent Literature 7 below).
A method of providing a contact of an n+ source layer also for a side wall of a trench has been proposed as another method. According to this method, the contact of the n+ source layer in the device surface portion does not affect contact resistance and therefore, the width of the n+ source layer along the direction of the trench width may be narrow. Therefore, finer processing is enabled (see, e.g., Patent Literature 8 below).
A method of forming a gate region in a two-stage trench to narrow the width of a unit cell that includes a source region and a gate region, aimed at reducing “Ron*A (ON-resistance per unit area)” has been proposed as another method (see, e.g., Patent Literature 9 and 10 below).
A method of forming a p-channel layer after forming a trench has been proposed as another method. According to this method, doping to form the p-channel layer is executed from a side wall of the trench. Thereby, control in forming the p-channel layer with respect to a trench gate electrode portion is improved (see, e.g., Patent Literature 11 below).
A semiconductor apparatus whose insulating layer under a gate electrode embedded in a trench is configured by a multi-layer insulating layer, aiming at reducing gate-drain capacity, has been proposed in, for example, Patent Literature 12 below.
A method of forming an n+ source layer similar to the method recited in Patent Literature 1 above is also proposed in, for example, Patent Literature 13 below. A semiconductor apparatus having a substantially identical structure as the semiconductor apparatus proposed in Patent Literature 2 above is also proposed in Patent Literature 3 to 13 above.